
DS1857
Dual Temperature-Controlled Resistors with
External Temperature Input and Monitors
____________________________________________________________________ 15
MEMORY
LOCATION
(hex)
EEPROM/
SRAM
SETTING
This alarm flag goes high when the lower limit
of the V
CC
setting is violated.
3——— MON1hi
This alarm flag goes high when the upper limit
of the MON1 setting is violated.
2——— MON1lo
This alarm flag goes high when the lower limit
of the MON1 setting is violated.
1——— MON2hi
This alarm flag goes high when the upper limit
of the MON2 setting is violated.
0——— MON2lo
This alarm flag goes high when the lower limit
of the MON2 setting is violated.
71 SRAM R — Alarm flags —
Bit 7 — — — X —
6——— X —
5——— X —
4——— X —
3——— X —
2——— X —
1——— X —
0——— MINT
A mask of all flags located in Table 01 byte
88h determines the value of MINT. MINT is
maskable to 0 if no interrupt is desired by
setting Table 01 byte 88h to 0.
72 to 7E SRAM R 00 Reserved —
7F SRAM
R/W
Table select —
Bit 7 — — 0 X —
6——0 X —
5——0 X —
4——0 X —
3——0 X —
2——0 X —
1——0
0——0
Table select bits
Set bits = 00 to select Table 00, set bits = 01
to select Table 01, set bits = 10 to select
Table 02, set bits = 11 to select Table 03.
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