
DS1501/DS1511 Y2KC Watchdog Real-Time Clocks
5 of 20
Figure 2. Write Cycle Timing, Write-Enable-Controlled
Figure 3. Write Cycle Timing, Chip-Enable-Controlled
t
WC
t
AH
t
DS
t
AS
t
WEZ
t
DH
t
WR
t
AS
DATA INPUT
DQ0–DQ7
E
E
A0–A4
DATA OUTPUT DATA INPUT
t
WEW
VALID VALID
t
WC
t
AH
t
DS
t
AS
t
DH
t
WR
t
AS
DATA INPUT
DQ0–DQ7
E
E
A0–A4
DATA INPUT
t
CEW
VALID VALID
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