
DS1338 I
2
C RTC with 56-Byte NV RAM
5 of 15
Figure 2. Timing Diagram
Figure 3. Block Diagram
RAM
(56 x 8)
SERIAL BUS
INTERFACE AND
DDRESS
REGISTER
OSCILLATOR AND
DIVIDER
CONTROL
LOGIC
X1
X2
SCL
SDA
1Hz
1Hz/4.096kHz/8.192kHz/32.768kHz
MUX/
BUFFER
SQW/OUT
USER BUFFER
(7 BYTES)
CLOCK,
CALENDAR,
ND CONTROL
REGISTERS
"C" VERSION
ONLY
POWER CONTROL
Dallas
Semiconductor
DS133
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