1 of 12 102199VBNCH1L1W1RSTCLKGND16151413121110912345678VCCNCSOUTW0H0L0COUTDQ16-Pin SOIC (300-mil)See Mech. Drawings SectionFEATURES Ultra-low power
DS126710 of 12 1021994. Relative linearity is used to determine the change in voltage between successive tap positions. Devicetest limits ±0.5 LSB.5.
DS126711 of 12 102199(C) END OF COMMUNICATION TRANSACTIONDIGITAL OUTPUT LOAD SCHEMATIC Figure 10
DS126712 of 12 102199TYPICAL SUPPLY CURENT VS. SERIAL CLOCK RATE Figure 11
DS12672 of 12 102199DESCRIPTIONThe DS1267 Dual Digital Potentiometer Chip consists of two digitally controlled, solid-statepotentiometers. Each potent
DS12673 of 12 102199DS1267 BLOCK DIAGRAM Figure 1I/O SHIFT REGISTER Figure 2Transmission of data always begins with the stack select bit followed by t
DS12674 of 12 102199STACKED CONFIGURATIONThe potentiometers of the DS1267 can be connected in series as shown in Figure 3. This is referred to asthe s
DS12675 of 12 102199The COUToutput of the DS1267 can be used to drive the DQ input of another DS1267. When connectingmultiple devices, the total numbe
DS12676 of 12 102199LINEARITY MEASUREMENT CONFIGURATION Figure 5NOTE:In this setup, a ±2% delta in total resistance R0 to R1 would cause a ±2.5 MI err
DS12677 of 12 102199INVERTING VARIABLE GAIN AMPLIFIER Figure 7FIX GAIN ATTENUATOR Figure 8
DS12678 of 12 102199ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground (VB=GND) -0.1V to +7.0VVoltage on Resistor Pins when VB=-5.5V -5.5V
DS12679 of 12 102199ANALOG RESISTOR CHARACTERISTICS (-40°C to +85°C; VCC = 5.0V ± 10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESEnd-to-End Resistor Tole
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