Rainbow-electronics AT26DF081A Manual do Utilizador

Features• Single 2.7V - 3.6V Supply• Serial Peripheral Interface (SPI) Compatible– Supports SPI Modes 0 and 3• 70 MHz Maximum Clock Frequency• Flexibl

103600H–DFLASH–11/2012AT26DF081Areset back to the logical “0” state if the program cycle aborts due to an incomplete address beingsent, an incomplete

113600H–DFLASH–11/2012AT26DF081A8.2 Sequential Program ModeThe Sequential Program Mode improves throughput over the Byte/Page Program commandwhen the

123600H–DFLASH–11/2012AT26DF081Asectors; therefore, once the highest unprotected memory location in a programming sequencehas been programmed, the dev

133600H–DFLASH–11/2012AT26DF081A8.3 Block EraseA block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single oper-a

143600H–DFLASH–11/2012AT26DF081AFigure 8-5. Block Erase8.4 Chip EraseThe entire memory array can be erased in a single operation by using the Chip Era

153600H–DFLASH–11/2012AT26DF081AFigure 8-6. Chip Erase9. Protection Commands and Features9.1 Write EnableThe Write Enable command is used to set the W

163600H–DFLASH–11/2012AT26DF081A9.2 Write DisableThe Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Reg-ister t

173600H–DFLASH–11/2012AT26DF081Aprogram and erase operations. In addition, the WEL bit in the Status Register will be reset backto the logical “0” sta

183600H–DFLASH–11/2012AT26DF081AUnprotect Sector command will be ignored, and the device will reset the WEL bit in the StatusRegister back to a logica

193600H–DFLASH–11/2012AT26DF081AEssentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector ProtectionRegisters are not lo

23600H–DFLASH–11/2012AT26DF081AThe AT26DF081A also offers a sophisticated method for protecting individual sectors againsterroneous or malicious progr

203600H–DFLASH–11/2012AT26DF081AIf the desire is to only change the SPRL bit without performing a Global Protect or Global Unpro-tect, then the system

213600H–DFLASH–11/2012AT26DF081AFigure 9-5. Read Sector Protection Register9.7 Protected States and the Write Protect (WP) PinThe WP pin is not linked

223600H–DFLASH–11/2012AT26DF081ATables 9-4 and 9-5 detail the various protection and locking states of the device.Note: 1. “n” represents a sector num

233600H–DFLASH–11/2012AT26DF081A10. Status Register Commands10.1 Read Status RegisterThe Status Register can be read to determine the device's re

243600H–DFLASH–11/2012AT26DF081A10.1.1 SPRL BitThe SPRL bit is used to control whether the Sector Protection Registers can be modified or not.When the

253600H–DFLASH–11/2012AT26DF081A10.1.6 WEL BitThe WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit isin the l

263600H–DFLASH–11/2012AT26DF081A10.2 Write Status RegisterThe Write Status Register command is used to modify the SPRL bit of the Status Registerand/o

273600H–DFLASH–11/2012AT26DF081A11. Other Commands and Functions11.1 Read Manufacturer and Device IDIdentification information can be read from the de

283600H–DFLASH–11/2012AT26DF081AFigure 11-1. Read Manufacturer and Device ID11.2 Deep Power-downDuring normal operation, the device will be placed in

293600H–DFLASH–11/2012AT26DF081AFigure 11-2. Deep Power-down11.3 Resume from Deep Power-downIn order exit the Deep Power-down mode and resume normal d

33600H–DFLASH–11/2012AT26DF081A2. Pin Descriptions and PinoutsTable 2-1. Pin DescriptionsSymbol Name and FunctionAssertedState TypeCSCHIP SELECT: Asse

303600H–DFLASH–11/2012AT26DF081A11.4 HoldThe HOLD pin is used to pause the serial communication with the device without having to stopor reset the clo

313600H–DFLASH–11/2012AT26DF081A12. Electrical Specifications12.1 Absolute Maximum Ratings*Temperature under Bias ... -5

323600H–DFLASH–11/2012AT26DF081ANotes: 1. Not 100% tested (value guaranteed by design and characterization).2. 15 pF load at 70 MHz, 30 pF load at 66

333600H–DFLASH–11/2012AT26DF081ANotes: 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles.2. Not 100% tested (value

343600H–DFLASH–11/2012AT26DF081A13. WaveformsFigure 13-1. Serial Input TimingFigure 13-2. Serial Output TimingFigure 13-3.HOLD Timing – Serial InputCS

353600H–DFLASH–11/2012AT26DF081AFigure 13-4. HOLD Timing – Serial OutputFigure 13-5. WP Timing for Write Status Register Command When SPRL = 1CSSISCKS

363600H–DFLASH–11/2012AT26DF081A14. Ordering Information14.1 Green Package Options (Pb/Halide-free/RoHS Compliant)fSCK(MHz) Ordering Code Package Oper

373600H–DFLASH–11/2012AT26DF081A15. Packaging Information15.1 8S1 – JEDEC SOICDRAWING NO. REV. TITLE GPCCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOL

383600H–DFLASH–11/2012AT26DF081A15.2 8S2 – EIAJ SOICTITLEDRAWING NO. GPCREV.Package Drawing Contact:[email protected] STN F 8S2, 8-lead, 0.

393600H–DFLASH–11/2012AT26DF081A16. Revision HistoryRevision Level – Release Date HistoryA – November 2005 Initial ReleaseB – March 2006Added Global P

43600H–DFLASH–11/2012AT26DF081A3. Block Diagram4. Memory ArrayTo provide the greatest flexibility, the memory array of the AT26DF081A can be erased in

Corporate OfficeCalifornia | USAAdesto Headquarters1250 Borregas AvenueSunnyvale, CA 94089 Phone: (+1) 408.400.0578Email: [email protected]© 2012

53600H–DFLASH–11/2012AT26DF081AFigure 4-1. Memory Architecture DiagramInternal Sectoring for64KB 32KB 4KB 1-256 ByteSector Protection Block Erase Bloc

63600H–DFLASH–11/2012AT26DF081A5. Device OperationThe AT26DF081A is controlled by a set of instructions that are sent from a host controller, com-monl

73600H–DFLASH–11/2012AT26DF081ANote: 1. Three address bytes are only required for the first operation to designate the address to start programming at

83600H–DFLASH–11/2012AT26DF081A7. Read Commands7.1 Read ArrayThe Read Array command can be used to sequentially read a continuous stream of data fromt

93600H–DFLASH–11/2012AT26DF081AFigure 7-2. Read Array – 03h Opcode8. Program and Erase Commands8.1 Byte/Page ProgramThe Byte/Page Program command allo