Rainbow-electronics AT83C24NDS Manual do Utilizador

Features• Smart Card Interface– Compliance with ISO 7816, EMV2000, GIE-CB, GSM and WHQL StandardsCard Clock Stop High or Low for Card Power-down Mo

104234F–SCR–10/05AT83C24 – over-current detection on CVCC– VCARDERR bit set in CONFIG0 register (out of range voltage on CVCC or bit set by software)

114234F–SCR–10/05 AT83C24CIO, CC4, CC8 ControllerThe CIO, CC4, CC8 output pins are driven respectively by CARDIO, CARDC4, CARDC8 bits values or by I/

124234F–SCR–10/05AT83C24 Figure 6. Clock Block Diagram with Software Activation (see page 14) Figure 7. Clock Block Diagram with Hardware Activati

134234F–SCR–10/05 AT83C24 Figure 8. CRST Block Diagram with soft activation Figure 9. CRST Block Diagram with Hardware Activation (CMDVCC pin used)

144234F–SCR–10/05AT83C24 Activation SequenceHardware Activation (DC/DC started with CMDVCC)Initial conditions: CARDDET bit must be configured in acco

154234F–SCR–10/05 AT83C24Software Activation (DC/DC Started With Writing in VCARD[1:0] bits) and ART bit = 1 Initial conditions: CARDRST bit = 0, CKS

164234F–SCR–10/05AT83C24 ISO 7816 constraints: ta = 200 card clock cycles 400 card clock cycles< = tb 400 card clock cycles< = tc < = 40000

174234F–SCR–10/05 AT83C24• VCARDERR bit is set by hardware (or by software)• INSERT is set and CARDIN is cleared (card extraction)• SHUTDOWN is set b

184234F–SCR–10/05AT83C24 Figure 14. Transparent Mode DescriptionPower Modes Two power-down modes are available to reduce the AT83C24 power consumpt

194234F–SCR–10/05 AT83C24Power Monitoring The AT83C24 needs only one power supply to run: VCC.If the microcontroller outputs signals with a different

24234F–SCR–10/05AT83C24 Acronyms TWI: Two-wire InterfacePOR: Power On ResetPFD: Power Fail DetectART: Automatic Reset TransitionATR: Answer To ResetM

204234F–SCR–10/05AT83C24 RegistersTable 6. CONFIG0 (Config Byte 0)7 6 5 4 3 2 1 01 0 ATRERR INSERT ICARDERR VCARDERR VCARD1 VCARD0Bit NumberBit Mnem

214234F–SCR–10/05 AT83C24Table 7. CONFIG 1 (Config Byte 1)7 6 5 4 3 2 1 0X ART SHUTDOWN CARDDET PULLUP CDS2 CDS1 CDS0Bit NumberBit MnemonicDescripti

224234F–SCR–10/05AT83C24 Notes: 1. When this register is changed, a special logic insures no glitch occurs on the CCLK pin and actual configuration c

234234F–SCR–10/05 AT83C24Table 9. CONFIG3 (Config Byte 3)7 6 5 4 3 2 1 0EAUTO VEXT1 VEXT0 ICCADJ LP X X XBit NumberBit MnemonicDescription7-5EAUTOVE

244234F–SCR–10/05AT83C24 Table 10. CONFIG4 (Config Byte 4)7 6 5 4 3 2 1 0X X X STEPREG INT_PULLUP POWERMON IT_SEL CRST_SELBit Number Bit Mnemonic De

254234F–SCR–10/05 AT83C24Table 11. INTERFACE (Interface Byte)7 6 5 4 3 2 1 00 IODIS CKSTOP CARDRST CARDC8 CARDC4 CARDCK CARDIOBit Number Bit Mnemoni

264234F–SCR–10/05AT83C24 Reset value = 0x00000001 Table 12. STATUS (Status Byte)7 6 5 4 3 2 1 0CC8 CC4 CARDIN VCARDOK X VCARD_INT CRST CIOBit Number

274234F–SCR–10/05 AT83C24Reset value = 0x10010000 Reset value = 0x00000000 Reset value = 0x00000000 Table 14. TIMER 0 (Timer LSB)7 6 5 4 3 2 1 0Bit

284234F–SCR–10/05AT83C24 Electrical CharacteristicsAbsolute Maximum Ratings *(**) Exposed die attached pad must be soldered to groundThermal resistor

294234F–SCR–10/05 AT83C24VOLOutput Low-voltage (I/O, C4, C8, PRES/INT)0.050.4VVIOL = -100 μAIOL = -1.2 mAVOHOutput High Voltage (C4, C8, PRES/INT)VOH

34234F–SCR–10/05 AT83C24Pin DescriptionPinouts (Top View) 28-pin SOIC Pinout QFN28 pinoutNote: 1. NC = Not Connected2. SOIC and QFN packages are avai

304234F–SCR–10/05AT83C24 Notes: 1. Capacitor: X7R type or X5R type, max ESR value is 30mΩ (100kHz-100MHz), Replacing 3.3µF by 2.2µF in parrallel wit

314234F–SCR–10/05 AT83C24Notes: 1. Capacitor: X7R type or X5R type, max ESR value is 30mΩ (100kHz-100MHz), Replacing 3.3µF by 2.2µF in parrallel wit

324234F–SCR–10/05AT83C24 Rise and Fall Slew rate0.20.12 V/nsCLASS A CCLK from 0.5 to 4.2VCLASS B CCLK from 0.5 to 0.85 x CVCCLow level voltage stabil

334234F–SCR–10/05 AT83C24Table 25. Smart Card RST (CRST pin) Symbol Parameter Min Typ Max Unit Test ConditionsVOLOutput Low-voltage000.12 x CVCC0.4

344234F–SCR–10/05AT83C24 Typical ApplicationFigure 1. Typical Standard Mode Application Diagram for 3 AT83C24 (up to 8 AT83C24 if needed)Note: 1. Th

364234F–SCR–10/05AT83C24 Typical NDS ApplicationFigure 2. Typical NDS Standard Mode Application Diagram for 1 AT83C24NDS.Note: 1. The external resis

374234F–SCR–10/05 AT83C24Ordering InformationPart Number Supply Voltage Temperature Range Package PackingAT83C24B-PRTIL(2)3V to 5.5V Industrial QFN

384234F–SCR–10/05AT83C24 Note: 1. Enhanced AC/DC parameters, see first page for differences between AT83C24 and AT83C24NDS.2. Refer to index mark for

394234F–SCR–10/05 AT83C24Package DrawingsQFN28

44234F–SCR–10/05AT83C24 SDA VCC3 kVI/Oopen-drain Microcontroller Interface FunctionTWI serial dataSCL VCC3 kVI/Oopen-drain Microcontroller Interface

SO28

414234F–SCR–10/05 AT83C24Datasheet Change LogChanges from 4234A-05/03 to 4234B-02/041. Addition of CRST, CIO, CCLK controllers descriptions, page 10.

Printed on recycled paper.4234F–SCR–10/05© Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, are registered tradema

54234F–SCR–10/05 AT83C24Note: ESD Test conditions: 3 positive and 3 negative pulses on each pin versus GND. Pulses generated according to Mil/STD 883

64234F–SCR–10/05AT83C24 Operational ModesTWI Bus Control The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made

74234F–SCR–10/05 AT83C24Address Byte The first byte to send to the device is the address byte. The device controls if the hardware address (A2/CK, A

84234F–SCR–10/05AT83C24 Write Commands The write commands are:1. Reset:Initializes all the logic and the TWI interface as after a power-up or power-f

94234F–SCR–10/05 AT83C24Read Command After the slave address has been configured, the read command allows to read one or several bytes in the follow