Rainbow-electronics AT90LS8535 Manual do Utilizador

1Features• AVR® – High-performance and Low-power RISC Architecture– 118 Powerful Instructions – Most Single Clock Cycle Execution– 32 x 8 General-purp

10AT90S/LS85351041H–11/01X-register, Y-register and Z-registerThe registers R26..R31 have some added functions to their general-purpose usage.These re

100AT90S/LS85351041H–11/01Figure 71. Serial Programming and VerifyFor the EEPROM, an auto-erase cycle is provided within the self-timed write instruc

101AT90S/LS85351041H–11/014. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a positi

102AT90S/LS85351041H–11/01fNotes: 1. a = address high bitsb = address low bitsH = 0 – Low byte, 1 – High Byteo = data outi = data inx = don’t care1 =

103AT90S/LS85351041H–11/01Serial Programming CharacteristicsFigure 73. Serial Programming TimingTable 43. Serial Programming Characteristics, TA = -

104AT90S/LS85351041H–11/01Electrical CharacteristicsAbsolute Maximum Ratings*Operating Temperature ... -40°C to +105°C*N

105AT90S/LS85351041H–11/01Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low (logical “0”).2. “Min” means the lowes

106AT90S/LS85351041H–11/01External Clock Drive WaveformsFigure 74. External ClockTable 46. External Clock DriveSymbol ParameterVCC = 2.7V to 6.0V VC

107AT90S/LS85351041H–11/01Typical CharacteristicsThe following charts show typical behavior. These figures are not tested during manu-facturing. All c

108AT90S/LS85351041H–11/01Figure 76. Active Supply Current vs. VCCFigure 77. Idle Supply Current vs. Frequency02468101214162 2.5 3 3.5 4 4.5 5 5.5 6

109AT90S/LS85351041H–11/01Figure 78. Idle Supply Current vs. VCCFigure 79. Power-down Supply Current vs. VCC012345672 2.5 3 3.5 4 4.5 5 5.5 6T = 25

11AT90S/LS85351041H–11/01SRAM Data Memory Figure 8 shows how the AT90S8535 SRAM memory is organized.Figure 8. SRAM OrganizationThe lower 608 data mem

110AT90S/LS85351041H–11/01Figure 80. Power-down Supply Current vs. VCCFigure 81. Power Save Supply Current vs. VCC0204060801001201402 2.5 3 3.5 4 4.

111AT90S/LS85351041H–11/01Figure 82. Analog Comparator Current vs. VCCNote: Analog comparator offset voltage is measured as absolute offset.Figure 83

112AT90S/LS85351041H–11/01Figure 84. Analog Comparator Offset Voltage vs. Common Mode VoltageFigure 85. Analog Comparator Input Leakage Current02468

113AT90S/LS85351041H–11/01Figure 86. Watchdog Oscillator Frequency vs. VCCNote: Sink and source capabilities of I/O ports are measured on one pin at

114AT90S/LS85351041H–11/01Figure 88. Pull-up Resistor Current vs. Input VoltageFigure 89. I/O Pin Sink Current vs. Output Voltage0510152025300 0.5 1

115AT90S/LS85351041H–11/01Figure 90. I/O Pin Source Current vs. Output VoltageFigure 91. I/O Pin Sink Current vs. Output Voltage024681012141618200 0

116AT90S/LS85351041H–11/01Figure 92. I/O Pin Source Current vs. Output VoltageFigure 93. I/O Pin Input Threshold Voltage vs. VCC05101520250 0.5 1 1.

117AT90S/LS85351041H–11/01Figure 94. I/O Pin Input Hysteresis vs. VCC00.020.040.060.080.10.120.140.160.182.7 4.0 5.0Input hysteresis (V)V ccI/O PIN I

118AT90S/LS85351041H–11/01Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page$3F ($5F) SREG I T H S V N Z C page 19$3E (

119AT90S/LS85351041H–11/01Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory ad

12AT90S/LS85351041H–11/01Program and Data Addressing ModesThe AT90S8535 AVR RISC microcontroller supports powerful and efficient addressingmodes for a

120AT90S/LS85351041H–11/01Instruction Set SummaryMnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add

121AT90S/LS85351041H–11/01LD Rd, Y Load Indirect Rd ← (Y) None 2LD Rd, Y+ Load Indirect and Post-inc. Rd ← (Y), Y ← Y + 1 None 2LD Rd, -Y Load Indirec

122AT90S/LS85351041H–11/01Ordering InformationPower Supply Speed (MHz) Ordering Code Package Operation Range2.7 - 6.0V 4 AT90LS8535-4ACAT90LS8535-4JCA

123AT90S/LS85351041H–11/01Packaging Information44A1.20(0.047) MAX10.10(0.394) 9.90(0.386)SQ12.25(0.482)11.75(0.462)SQ0.75(0.030)0.45(0.018)0.15(0.006

124AT90S/LS85351041H–11/0144J1.14(0.045) X 45˚PIN NO. 1IDENTIFY0.813(0.032)0.660(0.026)1.27(0.050) TYP12.70(0.500) REF SQ1.14(0.045) X 45˚0.51(0.020)M

125AT90S/LS85351041H–11/0140P652.71(2.075)51.94(2.045)PIN113.97(0.550)13.46(0.530)0.38(0.015)MIN0.56(0.022)0.38(0.015)REF15.88(0.625)15.24(0.600)1.65(

126AT90S/LS85351041H–11/0144M1 2325 Orchard Parkway San Jose, CA 95131TITLE44M1, 44-pad ,7 x 7 x 1.0 mm body, lead pitch 0.50mmMicro lead frame pac

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

13AT90S/LS85351041H–11/01Data Direct Figure 12. Direct Data AddressingA 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/R

14AT90S/LS85351041H–11/01Data Indirect with Pre-decrementFigure 15. Data Indirect Addressing with Pre-decrementThe X-, Y-, or the Z-register is decre

15AT90S/LS85351041H–11/01Indirect Program Addressing, IJMP and ICALLFigure 18. Indirect Program Memory AddressingProgram execution continues at addre

16AT90S/LS85351041H–11/01Figure 20. The Parallel Instruction Fetches and Instruction Executions Figure 21 shows the internal timing concept for the r

17AT90S/LS85351041H–11/01I/O Memory The I/O space definition of the AT90S8535 is shown in Table 1.Table 1. AT90S8535 I/O SpaceI/O Address (SRAM Addre

18AT90S/LS85351041H–11/01Note: Reserved and unused locations are not shown in the table.All AT90S8535 I/Os and peripherals are placed in the I/O space

19AT90S/LS85351041H–11/01Status Register – SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:• Bit 7 – I: Global Inter

2AT90S/LS85351041H–11/01Pin Configurations

20AT90S/LS85351041H–11/01Stack Pointer – SP The AT90S8535 Stack Pointer is implemented as two 8-bit registers in the I/O spacelocations $3E ($5E) and

21AT90S/LS85351041H–11/01The most typical and general program setup for the Reset and Interrupt vectoraddresses are:Address Labels Code Comments$000 r

22AT90S/LS85351041H–11/01placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 3defines the timing and electrical p

23AT90S/LS85351041H–11/01Figure 24. MCU Start-up, RESET Tied to VCC.Figure 25. MCU Start-up, RESET Controlled ExternallyExternal Reset An external r

24AT90S/LS85351041H–11/01Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura-tion. On the falling ed

25AT90S/LS85351041H–11/01Interrupt Handling The AT90S8535 has two 8-bit interrupt mask control registers: GIMSK (General Inter-rupt Mask register) and

26AT90S/LS85351041H–11/01sponding interrupt of External Interrupt Request 0 is executed from program memoryaddress $001. See also “External Interrupts

27AT90S/LS85351041H–11/01• Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt EnableWhen the TICIE1 bit is set (one) and the I-bit in the Status R

28AT90S/LS85351041H–11/01• Bit 5 – ICF1: Input Capture Flag 1The ICF1 bit is set (one) to flag an input capture event, indicating that theTimer/Counte

29AT90S/LS85351041H–11/01Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cyclesminimum. Four

3AT90S/LS85351041H–11/01Description The AT90S8535 is a low-power CMOS 8-bit microcontroller based on the AVR RISCarchitecture. By executing powerful i

30AT90S/LS85351041H–11/01The value on the INT pin is sampled before detecting edges. If edge interrupt isselected, pulses that last longer than one CP

31AT90S/LS85351041H–11/01Comparator Interrupt is not required, the Analog Comparator can be powered down bysetting the ACD-bit in the Analog Comparato

32AT90S/LS85351041H–11/01Timer/Counters The AT90S8535 provides three general-purpose Timer/Counters – two 8-bit T/Cs andone 16-bit T/C. Timer/Counter2

33AT90S/LS85351041H–11/01The clock source for Timer/Counter2 prescaler is named PCK2. PCK2 is by default con-nected to the main system clock (CK). By

34AT90S/LS85351041H–11/01Timer/Counter0 Control Register – TCCR0• Bits 7..3 – Res: Reserved BitsThese bits are reserved bits in the AT90S8535 and alwa

35AT90S/LS85351041H–11/0116-bit Timer/Counter1 Figure 31 shows the block diagram for Timer/Counter1.Figure 31. Timer/Counter1 Block DiagramThe 16-bit

36AT90S/LS85351041H–11/01the counter on compareA match and actions on the Output Compare pins on both com-pare matches.Timer/Counter1 can also be used

37AT90S/LS85351041H–11/01Note: X = A or B.In PWM mode, these bits have a different function. Refer to Table 15 for a detaileddescription. When changin

38AT90S/LS85351041H–11/01• Bit 3 – CTC1: Clear Timer/Counter1 on Compare MatchWhen the CTC1 control bit is set (one), the Timer/Counter1 is reset to $

39AT90S/LS85351041H–11/01TEMP, interrupts must be disabled during access from the main program (and frominterrupt routines if interrupts are allowed f

4AT90S/LS85351041H–11/01The AVR core combines a rich instruction set with 32 general-purpose working regis-ters. All the 32 registers are directly con

40AT90S/LS85351041H–11/01OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH orOCR1BH. Consequently, the high byte OCR1AH or OCR1B

41AT90S/LS85351041H–11/01up-counting and down-counting values are reached simultaneously. When the prescaleris in use (CS12..CS10 ≠ 001 or 000), the P

42AT90S/LS85351041H–11/01Note: X = AIn PWM mode, the Timer Overflow Flag1 (TOV1) is set when the counter advances from$0000. Timer Overflow Interrupt1

43AT90S/LS85351041H–11/01Timer/Counter Control Register (TCCR2). The interrupt enable/disable settings arefound in the Timer/Counter Interrupt Mask Re

44AT90S/LS85351041H–11/01When the prescaler is set to divide by 8, the timer will count like this:... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1,

45AT90S/LS85351041H–11/01Timer/Counter2 in PWM Mode When the PWM mode is selected, Timer/Counter2 and the Output Compare Register(OCR2) form an 8-bit,

46AT90S/LS85351041H–11/01In PWM mode, the Timer Overflow Flag (TOV2) is set when the counter advances from$00. Timer Overflow Interrupt2 operates exac

47AT90S/LS85351041H–11/01Asynchronous Operation of Timer/Counter2When Timer/Counter2 operates asynchronously, some considerations must be taken.• Warn

48AT90S/LS85351041H–11/01least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the

49AT90S/LS85351041H–11/01Watchdog Timer The Watchdog Timer is clocked from a separate On-chip oscillator. By controlling theWatchdog Timer prescaler,

5AT90S/LS85351041H–11/01current if the pull-up resistors are activated. Two Port C pins can alternatively be usedas oscillator for Timer/Counter2.The

50AT90S/LS85351041H–11/011. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to

51AT90S/LS85351041H–11/01EEPROM Read/Write AccessThe EEPROM access registers are accessible in the I/O space.The write access time is in the range of

52AT90S/LS85351041H–11/01• Bit 2 – EEMWE: EEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to “1” causes the EEPROM to bewritte

53AT90S/LS85351041H–11/01Prevent EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply volt-age is too low f

54AT90S/LS85351041H–11/01Serial Peripheral Interface – SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transferbetween the

55AT90S/LS85351041H–11/01Figure 38. SPI Master-slave InterconnectionThe system is single-buffered in the transmit direction and double-buffered in th

56AT90S/LS85351041H–11/01SS Pin Functionality When the SPI is configured as a master (MSTR in SPCR is set), the user can determinethe direction of the

57AT90S/LS85351041H–11/01Figure 40. SPI Transfer Format with CPHA = 1 and DORD = 0SPI Control Register – SPCR• Bit 7 – SPIE: SPI Interrupt EnableThis

58AT90S/LS85351041H–11/01• Bits 1,0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0These two bits control the SCK rate of the device configured as a maste

59AT90S/LS85351041H–11/01UART The AT90S8535 features a full duplex (separate receive and transmit registers) Univer-sal Asynchronous Receiver and Tran

6AT90S/LS85351041H–11/01Clock OptionsCrystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which canbe conf

60AT90S/LS85351041H–11/01is selected (the CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit inUCR is transferred to bit 9 in the Transm

61AT90S/LS85351041H–11/011 denote the first zero-sample. Following the 1-to-0 transition, the receiver samples theRXD pin at samples 8, 9 and 10. If t

62AT90S/LS85351041H–11/01UART ControlUART I/O Data Register – UDRThe UDR register is actually two physically separate registers sharing the same I/Oad

63AT90S/LS85351041H–11/01The FE bit is cleared when the stop bit of received data is one.• Bit 3 – OR: OverRunThis bit is set if an Overrun condition

64AT90S/LS85351041H–11/01Baud Rate Generator The baud rate generator is a frequency divider which generates baud rates according tothe following equat

65AT90S/LS85351041H–11/01UART Baud Rate Register – UBRRThe UBRR register is an 8-bit read/write register that specifies the UART Baud Rateaccording to

66AT90S/LS85351041H–11/01Analog Comparator The Analog Comparator compares the input values on the positive input PB2 (AIN0) andnegative input PB3 (AIN

67AT90S/LS85351041H–11/01• Bit 2 – ACIC: Analog Comparator Input Capture EnableWhen set (one), this bit enables the Input Capture function in Timer/Co

68AT90S/LS85351041H–11/01Analog-to-Digital ConverterFeature list • 10-bit Resolution• 0.5 LSB Integral Non-linearity• ±2 LSB Absolute Accuracy• 65 - 2

69AT90S/LS85351041H–11/01Operation The ADC converts an analog input voltage to a 10-bit digital value through successiveapproximation. The minimum val

7AT90S/LS85351041H–11/01Architectural OverviewThe fast-access register file concept contains 32 x 8-bit general-purpose working regis-ters with a sing

70AT90S/LS85351041H–11/01higher sampling rate. See “ADC Characteristics” on page 75 for more details. The ADCmodule contains a prescaler, which divide

71AT90S/LS85351041H–11/01Figure 48. ADC Timing Diagram, Single ConversionFigure 49. ADC Timing Diagram, Free Running ConversionADC Noise Canceler Fu

72AT90S/LS85351041H–11/012. Enter Idle Mode. The ADC will start a conversion once the CPU has been halted.3. If no other interrupts occur before the A

73AT90S/LS85351041H–11/01ADSC will read as one as long as a conversion is in progress. When the conversion iscomplete, it returns to zero. When a exte

74AT90S/LS85351041H–11/01• ADC9..0: ADC Conversion resultThese bits represent the result from the conversion. $000 represents analog ground and$3FF re

75AT90S/LS85351041H–11/01Notes: 1. Minimum for AVCC is 2.7V.2. Maximum for AVCC is 6.0V.ADC CharacteristicsTA = -40°C to 85°CSymbol Parameter Conditio

76AT90S/LS85351041H–11/01I/O Ports All AVR ports have true read-modify-write functionality when used as general digital I/Oports. This means that the

77AT90S/LS85351041H–11/01Port A as General Digital I/O All eight pins in Port A have equal functionality when used as digital I/O pins.PAn, general I/

78AT90S/LS85351041H–11/01Port B Port B is an 8-bit bi-directional I/O port.Three I/O memory address locations are allocated for the Port B, one each f

79AT90S/LS85351041H–11/01Port B As General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins.PBn, general I/

8AT90S/LS85351041H–11/01assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to beaccessed as though they were ordinary memory lo

80AT90S/LS85351041H–11/01allows analog signals that are close to VCC/2 to be present during power-down withoutcausing excessive power consumption.• AI

81AT90S/LS85351041H–11/01Figure 53. Port B Schematic Diagram (Pins PB2 and PB3)Figure 54. Port B Schematic Diagram (Pin PB4)DATA BUSDDQQRESETRESETCC

82AT90S/LS85351041H–11/01Figure 55. Port B Schematic Diagram (Pin PB5)Figure 56. Port B Schematic Diagram (Pin PB6)DATA BUSDDQQRESETRESETCCWDWPRDMOS

83AT90S/LS85351041H–11/01Figure 57. Port B Schematic Diagram (Pin PB7)DATA BUSDDQQRESETRESETCCWDWPRDMOSPULL-UPPB7RRWP:WD:RL:RP:RD:SPE:MSTRWRITE PORTB

84AT90S/LS85351041H–11/01Port C Port C is an 8-bit bi-directional I/O port.Three I/O memory address locations are allocated for the Port C, one each f

85AT90S/LS85351041H–11/01Alternate Functions of Port C When the AS2 bit in ASSR is set (one) to enable asynchronous clocking ofTimer/Counter2, pins PC

86AT90S/LS85351041H–11/01Figure 60. Port C Schematic Diagram (Pins PC7)Port D Port D is an 8-bit bi-directional I/O port with internal pull-up resist

87AT90S/LS85351041H–11/01Port D Data Register – PORTDPort D Data Direction Register – DDRDPort D Input Pins Address – PINDThe Port D Input Pins addres

88AT90S/LS85351041H–11/01• OC1A – Port D, Bit 5OC1A, Output compare matchA output: The PD5 pin can serve as an external output forthe Timer/Counter1 o

89AT90S/LS85351041H–11/01Port D Schematics Note that all port pins are synchronized. The synchronization latches are, however, notshown in the figures

9AT90S/LS85351041H–11/01memory. The different interrupts have priority in accordance with their interrupt vectorposition. The lower the interrupt vect

90AT90S/LS85351041H–11/01Figure 63. Port D Schematic Diagram (Pins PD2 and PD3)Figure 64. Port D Schematic Diagram (Pins PD4 and PD5)

91AT90S/LS85351041H–11/01Figure 65. Port D Schematic Diagram (Pin PD6)Figure 66. Port D Schematic Diagram (Pin PD7)DATA BUSDDQQRESETRESETCCWDWPRDMOS

92AT90S/LS85351041H–11/01Memory ProgrammingProgram and Data Memory Lock BitsThe AT90S8535 MCU provides two Lock bits that can be left unprogrammed (“1

93AT90S/LS85351041H–11/01Parallel Programming This section describes how to parallel program and verify Flash program memory,EEPROM data memory, Lock

94AT90S/LS85351041H–11/01Enter Programming Mode The following algorithm puts the device in Parallel Programming Mode:1. Apply supply voltage according

95AT90S/LS85351041H–11/01Chip Erase The Chip Erase command will erase the Flash and EEPROM memories and the Lockbits. The Lock bits are not reset unti

96AT90S/LS85351041H–11/011. Set BS to “1”. This selects high data.2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes

97AT90S/LS85351041H–11/01Figure 69. Programming the Flash Waveforms (Continued)Reading the Flash The algorithm for reading the Flash memory is as fol

98AT90S/LS85351041H–11/01Programming the Fuse Bits The algorithm for programming the Fuse bits is as follows (refer to “Programming theFlash” for deta

99AT90S/LS85351041H–11/01Parallel Programming CharacteristicsFigure 70. Parallel Programming TimingNotes: 1. Use tWLWH_CE for Chip Erase and tWLWH_PF